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data sheet october 1996 T7570 programmable pcm codec with hybrid-balance filter features n programmable internal hybrid-balance network n programmable transmit gain ?19.4 db range, 0.1 db step size n programmable receive gain ?19.4 db range, 0.1 db step size n dual-programmable pcm interface ?up to 64 time slots per frame ?variable data rate (64 khz to 4.096 mhz) ?two timing modes n programmable m -law or a-law companding n 300 w drive receive ampli?r n analog and digital loopbacks n on-chip sample-and-hold, autozero, and precision voltage reference n single 5 v power supply n latch-up free, low-power cmos technology ?70 mw typical operating power dissipation ?1.5 mw typical standby power dissipation n serial microprocessor-control interface n 6-pin parallel i/o latch n ttl- and cmos-compatible digital i/o n meets or exceeds d3/d4 (as per lucent pub 43801), itu-t (formerly ccitt) g.711?.714, and lssgr requirements n operating temperature range: ?0 c to +85 c description the lucent technologies microelectronics group T7570 programmable pcm codec with hybrid-bal- ance filter is a programmable pcm codec with an internal hybrid-balance network ?ter. it provides ana- log-to-digital and digital-to-analog conversion, as well as the transmit and receive ?tering necessary to interface a voice telephone circuit to a time-division multiplexed (tdm) system. programmable features include transmit gain setting over a 19.4 db range and receive gain setting over a 19.4 db range. an internal ?ter can be programmed to provide hybrid balancing over a wide range of loop impedances for both active and transformer subscriber line interface circuits (slic). the device is programmed over a low pin-count, standard, serial, microprocessor-control interface. a 6-pin parallel input/output latch is provided to control interface circuits. each of these pins can be individu- ally programmed to be an input or an output. the T7570 is fabricated by using a low-power cmos technology, requires a single 5 v supply, and is avail- able in a 28-pin plcc package for surface mounting.
2 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 table of contents content page features ................................................................................................................................................................... 1 description ............................................................................................................................................................... 1 pin information ......................................................................................................................................................... 3 functional description .............................................................................................................................................. 5 powerup initialization ............................................................................................................................................ 5 powerdown state .................................................................................................................................................. 5 transmit filter and encoder .................................................................................................................................. 5 decoder and receive filter .................................................................................................................................. 6 pcm interface ....................................................................................................................................................... 6 serial control port ................................................................................................................................................ 6 programmable functions ...................................................................................................................................... 7 hybrid-balance filter .......................................................................................................................................... 11 programming the filter ....................................................................................................................................... 12 absolute maximum ratings .................................................................................................................................... 13 handling precautions ............................................................................................................................................. 13 electrical characteristics ........................................................................................................................................ 14 dc characteristics ............................................................................................................................................... 14 transmission characteristics .................................................................................................................................. 15 timing characteristics ............................................................................................................................................ 20 applications ............................................................................................................................................................ 25 outline diagram ...................................................................................................................................................... 26 28-pin plcc ....................................................................................................................................................... 26 ordering information ............................................................................................................................................... 27
3 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter description (continued) 5-2786 (c) figure 1. block diagram pin information 5-2787 (c) figure 2. pin diagram hybrid balance filter v ref transmit filter analog loopback receive filter il5 il4 il3 il2 il1 il0 interface latches decoder ci co cclk control register rx register d r 0 d r 1 mclk mr fs x bclk fs r d x 0 d x 1 time-slot assign- ment az tx register vf r o digital loopback encoder ts x 0 ts x 1 cs vf x i ci cclk mr mclk bclk d x 0 cs 12 13 14 15 16 17 18 nc nc vf r o gnd v dd vf x i il0 5 6 7 8 9 10 11 nc il3 il2 fs r d r 1 d r 0 co il1 il4 il5 fs x d x 1 ts x 1 ts x 0 25 24 23 22 21 20 19 4 3 2 1 27 28 26 T7570 --- ml2
4 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 pin information (continued) table 1. pin description pin symbol type name/description 1 gnd ground . all analog and digital signals are referenced to this pin. 2vf r oo receive analog power ampli?r output. this pin can drive load impedances as low as 300 w . pcm data received on the assigned d r pin is decoded and appears at this output as a voice-frequency signal. 3nc no connect. connections may be made to or traces may be routed through this pin. 4 5 nc no connects. do not make connections to or route traces through pins 4 and 5. 6 7 il3 il2 i/o i/o interface latch i/o. these pins can be individually programmed as inputs or outputs as determined by the state of the corresponding bits in the latch direction register (ldr). for pins con?ured as inputs, the logic state sensed on each input is latched into the interface latch register (ilr) whenever control data is written to the T7570, and the information is shifted out on the co pin. when con?ured as outputs, control data written into the ilr appears at the corresponding il pins. 8fs r i receive frame-sync input. a pulse or square-wave waveform with an 8 khz repeti- tion rate is applied to this input to de?e the start of the receive time slot assigned to this device (nondelayed frame mode), or the start of the receive frame (delayed frame mode using the internal time-slot assignment counter). 9 10 d r 1 d r 0 i i receive pcm inputs. these receive data input(s) are inactive except during the assigned receive time slot of the assigned port when the receive pcm data is shifted in on the falling edges of bclk. 11 co o control output. serial control information is shifted out from the T7570 on this pin when is low. it can be connected to ci if required. 12 ci i control input. serial control information is shifted into the T7570 on this pin when is low. it can be connected to co if required. 13 cclk i control clock. this clock shifts serial control information into ci or out from co when the is low, depending on the current instruction. cclk can be asynchronous with the other system clocks. 14 i chip select (active-low). when this pin is low, control information can be written into or read from the T7570 via the ci and co pins. 15 mr i master reset. this logic input must be pulled low for normal operation of the T7570. when pulled momentarily high (at least 1 m s), all programmable registers in the device are reset to the states speci?d under powerup initialization. 16 bclk i bit clock input. this pin shifts pcm data into and out of the d r and d x pins. bclk can vary from 64 khz to 4.096 mhz in 8 khz increments and must be synchronous with mclk at the start of each frame. mclk can be used as bclk. 17 mclk i master clock. the master-clock input is used by the switched capacitor ?ters and the encoder and decoder sequencing logic. it must be 1.536 mhz, 1.544 mhz, 2.048 mhz, or 4.096 mhz and must be synchronous with bclk at the start of each frame. 18 19 d x 0 d x 1 o o transmit pcm output. these transmit-data, high-impedance state outputs remain in the high-impedance state except during the assigned transmit time slot on the assigned port, during which the transmit pcm data byte is shifted out on the rising edges of bclk. 20 21 x 0 x 1 o o backplane line driver enable (active-low). normally, these open-drain outputs are ?ating in a high-impedance state. when a time slot is active on one of the d x outputs, the appropriate x output pulls low to enable a backplane line driver. cs cs cs cs ts ts ts
5 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter pin information (continued) table 1. pin description (continued) pin symbol type name/description 22 fs x i transmit frame-sync input. a pulse or square-wave waveform with an 8 khz repetition rate is applied to this input to de?e the start of the transmit time slot assigned to this device (nondelayed frame mode) or the start of the transmit frame (delayed frame mode using the internal time-slot assignment counter). if only the receive chan- nel is being used, it is still necessary to apply the transmit frame- sync every frame. 23 24 25 26 il5 il4 il1 il0 i/o i/o i/o i/o interface latch. see pin 6. 27 v dd 5 v 5% power supply. 28 vf x ii transmit analog high-impedance input. voice-frequency signals present on this input are encoded as an a-law or m -law pcm bit stream and are shifted out on the selected d x pin. functional description powerup initialization when power is ?st applied, powerup reset circuitry ini- tializes the T7570 and puts it into the powerdown state. the gain control registers for the transmit and receive gain sections are programmed to off, the hybrid- balance circuit is turned off, the power amp is disabled, and the device is in the nondelayed timing mode. the latch direction register (ldr) is preset with all il pins programmed as inputs, placing the interface pins in a high-impedance state. the ci is ready for the ?st con- trol byte of the initialization sequence. other initial states in the control register are indicated in the control register instruction section under programmable functions. a reset to these same initial conditions can also be forced by driving the mr pin momentarily high for at least 1 m s. this can be done either on powerup or pow- erdown. for normal operation, this pin must be pulled low. the desired modes for all programmable functions can be initialized via the serial control port prior to a pow- erup command. powerdown state following a period of activity in the powerup state, the powerdown state can be entered by writing any of the control instructions into the serial control port with the p bit set to 1, as indicated in table 2. the powerdown instruction can be included within any other instruction code. it is recommended that the chip be powered down before executing any instructions. in the powerdown state, all nonessential circuitry is de- activated and the d x 0 and d x 1 outputs are in the high- impedance condition. the coef?ients stored in the hybrid-balance circuit and the gain control registers, the data in the ldr and ilr, and all control bits remain unchanged in the power- down state unless changed by writing new data via the serial control port, which remains active. the outputs of the interface latches also remain active, maintaining the ability to monitor and control interface circuits like a slic. transmit filter and encoder the transmit section input, vf x i, provides a high- impedance load to the line-interface circuit. the input signal is summed with the internal hybrid cancellation signal. the resulting signal is the input to a programma- ble gain or attenuation ampli?r that is controlled by the contents of the transmit gain register (see programma- ble functions section). the signal is then passed through an antialiasing ?ter followed by a ?th-order, low-pass and third-order, high-pass, switched-capacitor ?ter. after the ?ter, the a/d converter translates the signal into pcm data for transmission. the a/d
6 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 functional description (continued) transmit filter and encoder (continued) converter has a compressing characteristic according to the standard itu-t a- or m -coding laws selected by a control instruction (see tables 2 and 3). a precision on- chip voltage reference helps ensure accurate and highly stable transmission levels. any offset voltage arising in the gain-set ampli?r, the ?ters, or the com- parator is canceled by an internal autozero circuit. decoder and receive filter pcm data is shifted into the decoder's receive pcm register via the d r 0 or d r 1 pin during the selected time slot on eight falling edges of bclk. the decoder con- sists of an expanding digital-to-analog convertor with either a- or m -law decoding characteristic, which is selected by the same control instruction used to select the encode law. following the decoder is a ?th-order, low-pass, switched-capacitor ?ter with sin(x)/x correc- tion for the 8 khz sample and hold. a programmable gain ampli?r that is set by writing to the receive gain register is included, followed by a power ampli?r capa- ble of driving a 300 w load to 4.0 v peak to peak. pcm interface the fs x and fs r frame-sync inputs determine the beginning of the 8-bit transmit and receive time slots, respectively. they can have any duration from a single cycle of bclk high to one mclk period low. two differ- ent relationships can be established between the frame-sync inputs and the actual time slots on the pcm buses by setting bit 3 in the control register (see table 3). nondelayed data mode is similar to long- frame timing of other codecs for which time slots begin nominally coincident with the rising edge of the appro- priate fs input. the alternative is to use delayed-data mode in which each fs input must be high at least a half-cycle of bclk earlier than the time slot. the time- slot assignment circuit on the device can only be used with delayed-data timing. the time-slot assignment capability of this device is a subset of the lucent concentration highway interface. the beginning of the ?st time slot in a frame is identi- ?d by the appropriate fs input. the actual transmit and receive time slots are then determined by the inter- nal time-slot assignment counters. transmit and receive frames and time slots can be skewed from each other by any number of bclk cycles by offsetting fs r and fs x . during each assigned trans- mit time slot, the selected d x 0/1 output shifts data out from the pcm register on the rising edges of bclk. x 0 (or x 1 as appropriate) also pulls low for the ?st 7.5 bit times of the time slot to control the high- impedance state enable of a backplane line driver. serial pcm data is shifted into the selected d r 0/1 input during each assigned receive time slot on the falling edges of bclk. d x 0 or d x 1 and d r 0 or d r 1 are select- able on the T7570 (see the port selection section under programmable functions). serial control port programmable register instructions (table 2) are writ- ten into or read back from the T7570 via the serial con- trol port consisting of the control clock (cclk), the serial data input (ci) and output (co), and the chip- select input ( ) (see figure 6). all instructions require 2 bytes, with the exception of a single-byte powerup/powerdown command. the bits in byte 1 are de?ed as follows: bit 7 speci?s powerup or power- down; bits 6, 5, 4, and 3 specify the register address; bit 2 speci?s whether the instruction is a read or a write; bit 1 speci?s a one- or two-byte instruction; and bit 0 is not used. to shift control data into the T7570, cclk must be pulsed high eight times while is low. data on the ci input is shifted into the serial input register on the fall- ing edge of each cclk pulse. after all data is shifted in, the contents of the input shift register are decoded and can indicate that a second byte of control data follows. this second byte can either be de?ed by a second byte wide pulse or can follow the ?st con- tiguously; it is not mandatory for to return high between the ?st and second control bytes. at the end of the eighth cclk pulse in the second con- trol byte, the data is loaded into the appropriate pro- grammable register. can remain low continuously when programming successive registers, if desired. however, should be set high when no data trans- fers are in progress. to read back interface latch data or status information from the T7570, the ?st byte of the appropriate instruc- tion, as de?ed in table 2, is strobed in during the ?st pulse. must then be taken low for a further eight cclk cycles, during which the data is shifted onto the co pin on the rising edges of cclk. when is high, the co pin is in the high-impedance state, enabling the co pins of many devices to be multiplexed together. ts ts cs cs cs cs cs cs cs cs cs
7 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter functional description (continued) programmable functions any of the programmable registers can be modi?d while the device is powered up or down. powerup/powerdown control following powerup initialization, powerup and power- down control can be accomplished by writing any of the control instructions listed in table 2 into the T7570, with the p bit set to 0 for powerup or 1 for powerdown. nor- mally, it is recommended that all programmable func- tions be initially programmed while the device is powered down. power-state control can then be included with the last programming instruction or in a separate single-byte instruction. when the powerup or powerdown control is entered as a single-byte instruc- tion, bit 1 must be 0. when a powerup command is given, all deactivated circuits are activated, but the pcm outputs, d x 0 and d x 1, remain in the high-impedance state until the sec- ond fs x pulse after powerup. control register instruction the ?st byte of a read or write instruction to the control register is as shown in table 2. the second byte has the bit functions shown in tables 3, 5, 6, 7, 8, and 9. table 2. programmable register instructions notes: bit 7 of bytes 1 and 2 is always the ?st bit clocked into or out from the ci and co pins. x = don't care. p is the powerup/down control bit (0 = powerup, 1 = powerdown); see powerup/powerdown control section. other register address codes are invalid and should not be used. function byte 1 byte 2 pdn address r/w p2 x data 76543210 single-byte powerup/powerdown pxxxxx0x none write control register p 000001x see table 3. read control register p 000011x write interface latch register p 000101x see table 6. read interface latch register p 000111x write latch direction register p 001001x see table 5. read latch direction register p 001011x write receive gain register p 010001x see table 9. read receive gain register p 010011x write transmit gain register p 010101x see table 8. read transmit gain register p 010111x write hybrid-balance register 1 p 011001x these bits are de?ed by the lucent T7570 hybrid- balance software pro- gram. contact your lucent-me account rep- resentative for a copy of this software. read hybrid-balance register 1 p 011011x write hybrid-balance register 2 p 011101x read hybrid-balance register 2 p 011111x write hybrid-balance register 3 p 100001x read hybrid-balance register 3 p 100011x write receive time slot/port p 100101x see table 7. read receive time slot/port p 100111x (receive instruction) write transmit time slot/port p 101001x see table 7. read transmit time slot/port p 101011x(tr ansmit instruction)
8 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 functional description (continued) programmable functions (continued) control register instruction (continued) table 3. control register byte 2 functions * state at powerup initialization (bit 4 = 0). table 4. coding law conventions note: the msb is always the ?st pcm bit shifted in or out of the T7570. bit number and name function 76543210 f 1 f 0 ma ia dn dl al pp 0 0 reserved 0 1 mclk = 1.536 mhz or 1.544 mhz 1 0 mclk = 2.048 mhz* 1 1 mclk = 4.096 mhz 0 x m -law* 1 0 a-law, including even bit inversion 1 1 a-law, no even bit inversion 0 delayed data timing 1 nondelayed data timing* 0 0 nor mal operation* 1 x digital loopback 0 1 analog loopback 0power amp enabled in powerdown 1power amp disabled in powerdown* v in m -law msb lsb true a-law with even bit inversion msb lsb a-law without even bit inversion msb lsb v in = + full scale v in = 0 v v in = ?full scale 10000000 11111111 00000000 10101010 11010101 00101010 111111111 10000000 01111111 master clock frequency selection a master clock must be provided to the T7570 for oper- ation of the ?ter and coding/decoding functions. the mclk frequency must be either 1.536 mhz, 1.544 mhz, 2.048 mhz, or 4.096 mhz and must be synchronous with bclk at the start of each frame. bits f 0 and f 1 (see table 3) must be set during initialization to select the correct internal divider. coding law selection bits ma and ia in table 3 permit the selection of m -law coding or a-law coding, with or without even bit inver- sion. analog loopback the analog loopback mode is entered by setting the al and dl bits in the control register as shown in table 3. in the analog loopback mode, the transmit input vf x i is isolated from the input pin and internally connected to the vf r o output, forming a loop from the receive pcm register back to the transmit pcm register. the vf r o pin remains active, and the programmed settings of the transmit and receive gains remain unchanged; there- fore, care must be taken to ensure that overload levels are not exceeded anywhere in the loop. it is recom- mended that the hybrid-balance ?ter be disabled dur- ing analog loopback.
9 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter functional description (continued) programmable functions (continued) digital loopback the digital loopback mode is entered by setting the al and dl bits in the control register as shown in table 3. this mode provides another stage of path veri?ation by enabling data written into the receive pcm register to be read back from that register in any transmit time slot at d x 0/1. in digital loopback mode, the decoder remains functional and outputs a signal at vf r o. if this is undesirable, the receive output can be disabled by programming the receive gain register to all 0s. interface latch directions immediately following powerup, all interface latches assume they are inputs and, therefore, all il pins are in a high-impedance state. each il pin can be individually programmed as a logic input or output by writing the appropriate instruction to the ldr (see tables 2 and 5). for minimum power dissipation, unconnected latch pins should be programmed as outputs. bits l 5 ? 0 must be set by writing the speci?d instruc- tion to the ldr with the l bits in the second byte set as follows. table 5. byte 2 functions of latch direction register note: x = don't care. interface latch states interface latches con?ured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the interface latch register (ilr) as shown in tables 2 and 6. latches con?ured as inputs sense the state applied by an external source, such as the off-hook detect output of a slic. all bits of the ilr, i.e., sensed inputs and the pro- grammed state of outputs, can be read back in the sec- ond byte of a read of the ilr. it is recommended that during initialization, the state of il pins to be con?ured as outputs should be pro- grammed ?st, followed immediately by the ldr. table 6. interface latch data bit order bit number time-slot assignment the T7570 can operate in either ?ed time-slot or time- slot assignment mode for selecting the transmit and receive pcm time slots. following powerup, the device is automatically in nondelayed timing mode, in which the time slot always begins with the leading (rising) edge of frame-sync inputs fs x and fs r . time-slot assignment can only be used with delayed-data timing (see figure 5). fs x and fs r can have any phase rela- tionship with each other in bclk period increments. alternatively, the internal time-slot assignment counters and comparators can be used to access any time slot in a frame by using the frame-sync inputs as marker pulses for the beginning of transmit and receive time slots of 8 bits each. a time slot is assigned by a 2-byte instruction as shown in tables 2 and 7. the last 6 bits of the second byte indicate the selected time slot from 0 to 63 using straight binary notation. a new assign- ment becomes active on the second frame following the end of the for the second control byte. the en bit allows the pcm inputs, d r 0/1, or outputs, d x 0/1, as appropriate, to be enabled or disabled. time-slot assignment mode requires that the fs x and fs r pulses must conform to the delayed-data timing format shown in figure 5. port selection two transmit serial pcm ports, d x 0 and d x 1, and two receive serial pcm ports, d r 0 and d r 1, are provided to enable two-way space switching to be implemented. port selections for transmit and receive are made within the appropriate time-slot assignment instruction using the ps bit in the second byte. port selection can only be used in delayed-data timing mode. table 7 shows the format of the second byte of both transmit and receive time-slot and port assignment instructions. byte 2 bit number 76543210 l 0 l 1 l 2 l 3 l 4 l 5 xx l n bit il direction 0 input 1 output bit number 76543210 d 0 d 1 d 2 d 3 d 4 d 5 xx cs
10 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 functional description (continued) programmable functions (continued) table 7. time-slot and port assignment instruction * t 5 is the msb of the time-slot assignment. bit number and name 76543210 en ps t 5 * t 4 t 3 t 2 t 1 t 0 function 0 0xxxxxx disable d x 0 output (transmit instruction) disable d r 0 input (receive instruction) 0 1xxxxxx disable d x 1 output (transmit instruction) disable d r 1 input (receive instruction) 1 0 assign one binary-coded time slot from 0?3 enable d x 0 output (transmit instruction) enable d r 0 input (receive instruction) 1 1 assign one binary-coded time slot from 0?3 enable d x 1 output (transmit instruction) enable d r 1 input (receive instruction) transmit gain instruction byte 2 the transmit gain can be programmed in 0.1 db steps from ?.4 db to +19.0 db by writing to the transmit gain register as de?ed in tables 2 and 8. this corresponds to a range of 0 dbm0 levels at vf x i between 0.811 vrms and 0.087 vrms (equivalent to +0.4 dbm to ?9.0 dbm into 600 w ). to set transmit gain, determine the gain required of the codec in order to achieve the overall desired transmis- sion level point (tlp) at the pcm interface (usually 0 dbm or ? dbm). in order for the internal hybrid-balance circuitry to be effective, the portion of vf r o returned to the codec analog input must be between ?.5 db to ?0.25 db of the vf r o output. for instance, if a slic presents a ? dbm signal to vf x i when vf r o produces 0 dbm, good hybrid balance can be achieved. if the returned signal requires ampli?ation to satisfy this requirement, then an additional op amp in the transmit path would be required. the T7570 will accommodate the phase inversion. a spare op amp is provided in some lucent slics. once the codec gain is chosen, determine what signal level at vf x i would provide the desired tlp output at dx. for our example of +6 db gain (gx) providing a 0 dbm tlp and working backwards from dx, take the antilog of minus 6 db divided by 20 and multiply by the 0.7746 reference level to obtain the signal level at vf x i in vrms. as follows: (1) antilog 10 (?x / 20) * 0.7746 = vrms finally, convert the signal level to a decimal number (n) using the following formula: (2) 200 * log 10 (vrms / 0.08592) = n round n to the nearest integer and convert to binary. this is the code required by byte 2 of this instruction. some examples are given in table 8. table 8. byte 2 of transmit gain instructions * 0 db path gain setting. ?programming values greater than those listed in this table are permitted. however, large signals may cause overload. receive gain instruction byte 2 the receive gain can be programmed in 0.1 db steps from ?7.3 db to +2.1 db by writing to the receive gain register as de?ed in tables 2 and 9. this corresponds to a range of 0 dbm0 levels at vf r o between 0.987 vrms and 0.106 vrms (equivalent to +2.1 dbm to ?7.3 dbm into 600 w ). bit number 0 dbm0 test level (vrms) 7 6 5 4 3 2 1 0 at vf x i 0 0 0 0 0 0 0 0 no output 0 0 0 0 0 0 0 1 0.087 0 0 0 0 0 0 1 0 0.088 1 0 1 1 1 1 1 1* 0.7746 1 1 0 0 0 0 1 0 0.802 1 1 0 0 0 0 1 1 ? 0.811
11 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter functional description (continued) programmable functions (continued) to set receive gain, ?st determine the gain required of the codec. for line card use, determine the codecs allocation to set the overall transmission level point (tlp) at tip\ring accordingly (usually 0 dbm or ? dbm). once the codec gain is chosen, determine the signal level that would be delivered to vf r o when the refer- ence tlp appears at d r . take the antilog of the gain in db (g r ) divided by 20 and multiply by the 0.7746 refer- ence level to obtain the signal level at vf r o in vrms. as follows: (3) antilog 10 (g r / 20) * 0.7746 = vrms finally, convert the signal level output to a decimal number (n) using the following formula: (4) 200 * log 10 (vrms / 0.1045) = n round n to the nearest integer and convert to binary. this is the code required by byte 2 of this instruction. some examples are given in table 9. table 9. byte 2 of receive gain instructions * 0 db path gain setting. ?programming values greater than those listed in this table are permitted. however, large signals may cause overload. hybrid-balance filter the hybrid-balance ?ter on the T7570 is a programma- ble ?ter consisting of a second-order section, hybal1, followed by a ?st-order section, hybal2, and a pro- grammable attenuator. either of the ?ter sections can be bypassed if only one is required to achieve good cancellation. a selectable 180 inverting stage is included to compensate for interface circuits that invert the transmit input relative to the receive output signal. the second-order section is intended mainly to balance bit number 0 dbm0 test level (vrms) 7 6 5 4 3 2 1 0 at vf r i 0 0 0 0 0 0 0 0 no output (low z to gnd) 0 0 0 0 0 0 0 1 0.106 0 0 0 0 0 0 1 0 0.107 1 0 1 0 1 1 1 0* 0.7746 1 1 0 0 0 0 1 0 0.975 1 1 0 0 0 0 1 1 ? 0.987 low-frequency signals across a transformer slic, and the ?st-order section is intended to balance midrange to higher audio-frequency signals. as a second-order section, hybal1 has a pair of low- frequency zeros and a pair of complex conjugate poles. when con?uring the hybal1, matching the phase of the hybrid at low- to midband frequencies is most critical. once the echo path is correctly balanced in phase, the magnitude of the cancellation signal can be corrected by the programmable attenuator. the second-order mode of hybal1 is most suitable for balancing interfaces with transformers having high inductance of 1.5 h or more. an alternative con?ura- tion for smaller transformers is available by converting hybal1 to a simple ?st-order section with a single real low-frequency pole and zero. in this mode, the pole/zero frequency can be programmed. many line interfaces can be adequately balanced by use of the hybal1 ?ter only, in which case the hybal2 ?ter should be deselected to bypass it. hybal2, the higher-frequency ?st-order section, is pro- vided for balancing an electronic slic and is also help- ful with a transformer slic in providing additional phase correction for mid- and high-band frequencies, typically 1 khz to 3.4 khz. such a correction is particu- larly useful if the test balance impedance includes a capacitor of 100 nf or less, such as the loaded and nonloaded loop test networks in the united states. independent placement of the pole and zero location is provided. figure 3 shows a simpli?d diagram of the local echo- path for a typical application with a transformer inter- face. the magnitude and phase of the local echo sig- nal, measured at vf x i, are a function of the termination impedance z t , the line transformer, and the impedance of the two-wire loop, z l . if the impedance re?cted back into the transformer primary is expressed as z l ' , then the echo path transfer function from vf r o to vf x i is the following: (5) h(w) = z l ' /(z t + z l ' ) the signal level returned at vf x i must be between ?.5 db to ?0.25 db over the voice band, relative to the output at vf r o, in order for the hybrid balance function to be effective. signals outside this range exceed the range of programmability of the hybrid path, and the software will provide unacceptable hybrid balance performance over the voice band.
12 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 functional description (continued) hybrid-balance filter (continued) 5-2788 (c) figure 3. block diagram hybrid-balance filter network tip ring z l z l ' z t vf x i vf r o + to tx gain block hybal2 1st-order hi freq. filter (reg 3) hybal1 1st- or 2nd-order filter (reg 2) 1 from rx gain block attenuator gain r vfxi 2.4 +2.4 sel inv sel 2 set in reg 2 programming the filter on initial powerup, the hybrid-balance ?ter is disabled. before the hybrid-balance ?ter can be programmed, it is necessary to design the transformer and termination impedance to meet system 2-wire input return loss speci?ations, which are normally measured against a ?ed test impedance (600 w or 900 w in most coun- tries). only then can the echo path be modeled and the hybrid-balance ?ter programmed. hybrid balancing is also measured against a ?ed test impedance, speci- ?d by each national telecommunication administration to provide adequate control of talker and listener echo over the majority of their network connections. this test impedance is z l in figure 3. the echo signal and the degree of transhybrid loss obtained by the programma- ble ?ter must be measured from the pcm digital input, d r 0/1, to the pcm digital output, d x 0/1, either by digital test signal analysis or by conversion back to analog by a pcm codec/?ter. three registers must be programmed in the T7570 to fully con?ure the hybrid-balance ?ter (refer to table 2 for byte 1 addressing): register 1: select/deselect hybrid-balance ?ter; invert/noninvert cancellation signal; select/deselect hybal2 ?ter section; set attenuator. register 2: select/deselect hybal1 ?ter; set hybal1 to biquad or ?st order; select pole and zero frequency. register 3: program pole frequency in hybal2 ?ter; program zero frequency in hybal2 ?ter. standard ?ter design techniques can be used to model the echo path (see equation 5) and design a matching hybrid-balance ?ter con?uration. alternatively, the fre- quency response of the echo path can be measured and the hybrid-balance ?ter designed to replicate it. T7570 hybrid-balance software is available from your lucent account representative to aid in selecting the best balance ?ter register settings. byte 2 of register 1 76 5 43210 sel inv sel2 gain (all ? = max)
13 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter functional description (continued) hybrid-balance filter (continued) power supply while the pins of the T7570 devices are well protected against electrical misuse, it is recommended that the stan- dard cmos practice of applying gnd to the device before any other connections are made should always be fol- lowed. in applications where the printed-circuit card can be plugged into a hot socket with power and clocks already present, an extra-long ground pin on the connector should be used. to minimize noise sources, all ground connections to each device should meet at a common point as close as pos- sible to the device gnd pin to prevent the interaction of ground return currents ?wing through a common-bus impedance. a power-supply decoupling capacitor of 0.1 m f should be connected from this common point to v dd, as close to the device pins as possible. the power supply should also be decoupled with a low, effective series resis- tance capacitor of at least 10 m f, located near the card edge connector. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and a charged-device model (cdm) for esd susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to de?e the model. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and therefore can be used for comparison purposes. the hbm esd threshold presented here was obtained using these circuit parameters. table 10. human-body model esd threshold parameter symbol min max unit storage temperature range t stg ?5 150 c power supply voltage v dd 6.5 v voltage on any pin with respect to ground ?.5 0.5 + v dd v maximum power dissipation (package limit) p diss 600 mw device voltage T7570 3 2000 v
14 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 electrical characteristics for all tests, t a = ?0 c to +85 c, v dd = 5 v 5%, and gnd = 0 v, unless otherwise noted. typical values are for t a = 25 c and nominal supply values. dc characteristics table 11. digital interface table 12. power dissipation parameter symbol test conditions t a ( c) min max unit input voltage low v il all digital inputs 0.7 v high v ih all digital inputs 2.0 v output voltage low v ol d x 0, d x 1, co, i l = 3.2 ma 0.4 v all other digital outputs, i l = ? ma 0.4 v high v oh d x 0, d x 1, co, i l = 3.2 ma 2.4 v all other digital outputs except x , i l = ? ma 2.4 v all digital outputs, i l = ?00 m av cc ?0.5 v input current low i il any digital input, gnd < v in < v il ?0 10 m a high i ih any digital input except mr, v ih < v in < v cc ?0 10 m a mr only ?0 100 m a output current in high- impedance state i oz d x 0, d x 1, co, il5?l0 when selected as inputs, gnd < v out < v cc ?0 to 0 ?0 30 m a 0 to 85 ?0 10 m a parameter symbol test conditions typ max unit powerdown current i dd 0 cclk, ci, co = 0.4 v, = 2.4 v, interface latches set as outputs with no load, all other inputs active, power amp disabled 0.3 0.9 ma powerup current i dd 1 cclk, ci, co = 0.4 v, = 2.4 v, no load on power amp, interface latches set as outputs with no load 14.0 20.0 ma powerdown current i dd 2 cclk, ci, co = 0.4 v, = 2.4 v, interface latches set as outputs with no load, all other inputs active, power amp disabled, no load on power amp 4.0 6.0 ma ts cs cs cs
15 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter transmission characteristics table 13. analog interface table 14. gain and dynamic range parameter symbol test conditions min typ max unit input resistance r vfxi 0.25 v < vf x i < 4.75 v 390 585 k w input offset voltage at vf x ivos x 2.3 2.5 v load resistance rl vfro 300 w load capacitance cl vfro rl vfro 3 300 w cl vfro from vf r o to gnd 200 pf output resistance ro vfro steady zero pcm code applied to d r 0 or d r 1 1.6 3.0 w output offset voltage at vf r o vos r alternating zero pcm code applied to d r 0 or d r 1, maximum receive gain 2.3 2.5 v output offset voltage at vf r o, powerdown vos rpd control register byte 2, bit 7 = 0 2.3 2.5 v output voltage swing v swr rl = 300 w , maximum receive gain 4.01 v pp parameter symbol test conditions t a ( c) min typ max unit absolute levels g al maximum 0 dbm0 levels: vf x i (gain set to 11000011) 0.811 vrms vf r o (gain set to 11000011) 0.987 vrms minimum 0 dbm0 levels: vf x i (gain set to 00000001) 87.0 mvrms vf r o (gain set to 00000001) 106.0 mvrms transmit gain g xa transmit gain programmed for maximum 0 dbm0 test level, measured deviation of digital code from ideal 0 dbm0 pcm code at d x 0/1, t a = 25 c ?.15 0.15 db absolute accuracy transmit gain variation with temperature g xat measured relative to g xa , v dd = 5 v, minimum gain < g x < maximum gain ?0 to 0 ?.15 0.15 db 0 to 85 ?.1 0.1 db transmit gain variation with programmed gain g xag measured transmit gain over the range from maximum to minimum, calculated the devia- tion from the programmed gain relative to g xa (i.e., g xaf = g actual ?g prog ?g xa ), t a = 25 c, v dd = 5 v ?.1 0.1 db
16 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 transmission characteristics (continued) table 14. gain and dynamic range (continued) parameter symbol test conditions t a ( c) min typ max unit transmit gain variation with frequency g xaf relative to 1020 hz, minimum gain < g x < maximum gain, d r 0 or d r 1 = 0 dbm0 code: f = 16.67 hz ?5 ?0 db f = 50 hz ?3 ?0 db f = 60 hz ?0 ?0 db f = 200 hz ?.8 ?.5 0 db f = 300 hz to 3000 hz ?.125 0.04 0.125 db f = 3140 hz ?.57 0.01 0.125 db f = 3380 hz ?.885 ?.6 0.012 db f = 3860 hz ?.9 ?.98 db f 3 4600 hz (measured response at alias frequency from 0 khz to 4 khz) ?2 db transmit gain variation with signal level g xal sinusoidal test method, refer- ence level = 0 dbm0: vf x i = ?0 dbm0 to +3 dbm0 ?.2 0.2 db vf x i = ?0 dbm0 to ?0 dbm0 ?.4 0.4 db vf x i = ?5 dbm0 to ?0 dbm0 ?.2 1.2 db receive gain absolute accuracy g ra receive gain programmed for maximum 0 dbm0 test level, applied 0 dbm0 pcm code to d r 0 or d r 1, measured vf r o, t a = 25 c, load = 10 k w ?.15 0.15 db receive gain variation with temperature g rat measured relative to g ra , v dd = 5 v, minimum gain < g r < maxi- mum gain ?0 to 0 ?.15 0.15 db 0 to 85 ?.1 0.1 db receive gain variation with programmed gain g rag measured receive gain over the range from maximum to mini- mum setting, calculated the deviation from the programmed gain relative to g ra , i.e., g rag = g actual ?g prog ?g ra , t a = 25 c, v dd = 5 v ?.1 0.1 db
17 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter transmission characteristics (continued) table 14. gain and dynamic range (continued) table 15. envelope delay distortion parameter symbol test conditions t a ( c) min typ max unit receive gain variation with frequency g raf relative to 1020 hz, d r 0 or d r 1 = 0 dbm0 code, minimum gain < g r < maximum gain: f 3000 hz ?.125 0.04 0.125 db f = 3140 hz ?.57 0.01 0.125 db f = 3380 hz ?.885 ?.58 +0.012 db f = 3860 hz ?0.7 ?.98 db f 3 4600 hz ?8 db receive gain variation with signal level g ral sinusoidal test method, reference level = 0 dbm0: d r 0 = ?0 dbm0 to +3 dbm0 ?.2 0.2 db d r 0 = ?0 dbm0 to ?0 dbm0 ?.4 0.4 db d r 0 = ?5 dbm0 to ?0 dbm0 ?.2 1.2 db parameter symbol test conditions min max unit tx delay, absolute d xa f = 1600 hz 315 m s tx delay, relative to 1600 hz d xr f = 500 hz?00 hz 220 m s f = 600 hz?00 hz 145 m s f = 800 hz?000 hz 75 m s f = 1000 hz?600 hz 40 m s f = 1600 hz?600 hz 75 m s f = 2600 hz?800 hz 105 m s f = 2800 hz?000 hz 155 m s rx delay, absolute d ra f = 1600 hz 200 m s rx delay, relative to 1600 hz d rr f = 500 hz?000 hz ?0 m s f = 1000 hz?600 hz ?0 m s f = 1600 hz?600 hz 90 m s f = 2600 hz?800 hz 125 m s f = 2800 hz?000 hz 175 m s
18 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 transmission characteristics (continued) table 16. noise * ppsr x is measured with a ?0 dbm0 activation signal applied to vf x i. parameter symbol test conditions min typ max unit transmit noise, c message weighted, m -law selected n xc all 1s in gain register 15 dbrnc0 transmit noise, p message weighted, a-law selected n xp all 1s in gain register ? ?7 dbm0p receive noise, c message weighted, m -law selected n rc pcm code is alternating positive and negative zeros 13 dbrnc0 receive noise, p message weighted, a-law selected n rp pcm code equals positive one lsb ? ?9 dbm0p noise, single frequency n rs f = 0 khz?00 khz, analog to analog measurement (d x 0 is externally con- nected to d r 0), vf x i = 0 vrms ? ?3 dbm0 power supply rejection, transmit ppsr x v dd = 5.0 vdc + 100 mvrms: f = 0 khz? khz* f = 4 khz?0 khz 36 30 dbc dbc power supply rejection, receive ppsr r pcm code equals positive one lsb, v dd = 5.0 + 100 mvrms, measured vf r o: f = 0 hz?000 hz 36 dbc f = 4 khz?5 khz 40 db f = 25 khz?0 khz 36 db spurious out-of-band signals at the channel output sos 0 dbm0, 300 hz?400 hz input pcm code applied at d r 0 (or d r 1): 4600 hz?600 hz ?0 db 7600 hz?400 hz ? ?0 db 8400 hz?0,000 hz ? ?0 db
19 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter transmission characteristics (continued) table 17. distortion table 18. crosstalk * ct r? and ppsr x are measured with a ?0 dbm0 activation signal applied to vf x i. parameter symbol test conditions min max unit signal to total distortion std x sinusoidal test method level: transmit or receive std r 3.0 dbm0 33 dbc half-channel, m -law selected 0 dbm0 to ?0 dbm0 36 dbc ?0 dbm0 30 dbc ?5 dbm0 25 dbc single frequency distortion, transmit sfd x ? ?6 db single frequency distortion, receive sfd r ?6 db intermodulation distortion imd transmit or receive two frequencies in the range (300 hz?400 hz) ?1 db parameter symbol test conditions typ max unit transmit to receive crosstalk, 0 dbm0 transmit level ct x? f = 300 hz?400 hz d r = steady pcm code ?0 ?5 db receive to transmit crosstalk, 0 dbm0 receive level ct r? f = 300 hz?400 hz* ?0 ?0 db
20 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 timing characteristics a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purposes of this speci? cation, the following conditions apply: n all input signals are de?ed as v il = 0.4 v, v ih = 2.7 v, t r < 10 ns, t f < 10 ns. n t r is measured from v il to v ih . t f is measured from v ih to v il . n delay times are measured from the input signal valid to the output signal valid. n setup times are measured from the data input valid to the clock input invalid. n hold times are measured from the clock signal valid to the data input invalid. n pulse widths are measured from v il to v il or from v ih to v ih . table 19. master clock timing (see figures 4 and 5.) symbol parameter test conditions min typ max unit fmclk frequency of mclk?election frequency is programmable (see table 3.) 1536 1544 2048 4096 khz khz khz khz tmchmcl time of mclk high measured from v ih to v ih 80 ns tmclmch time of mclk low measured from v il to v il 80 ns tmch1mch2 rise time of mclk measured from v il to v ih 30 ns tmcl2mcl1 fall time of mclk measured from v ih to v il 30 ns tbclmch hold time, bclk low to mclk high ?0ns tfslfsh period of fs x or fs r low measured from v il to v il 1 mclk period
21 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter timing characteristics (continued) table 20. pcm interface timing (see figures 4 and 5.) symbol parameter test conditions t a ( c) min max unit fbclk frequency of bclk (can vary from 64 khz to 4096 khz in 8 khz increments) 64 4096 khz tbchbcl time of bclk high measured from v ih to v ih ?0ns tbclbch time of bclk low measured from v il to v il ?0ns tbch1bch2 rise time of bclk measured from v il to v ih 30 ns tbcl2bcl1 fall time of bclk measured from v ih to v il 30 ns tbclfxl tbclfrl hold time, bclk low fs x/r to high or low 30 ns tfxhbcl tfrhbcl setup time fs x/r , high to bclk low 30 ns tbchdxv delay time, bclk high to data valid load = 100 pf plus two lsttl loads 90 ns tbcldxz delay time, bclk low to d x 0/1 disabled if fs x low, fs x low to d x 0/1 disabled if eighth bclk low, or bclk high to d x 0/1 disabled if fs x high ?0 to 0 10 80 ns 0 to 85 15 80 ns tbchtxl delay time, bclk high to x low if fs x high, or fs x high to x low if bclk high load = 100 pf plus two lsttl loads 60 ns tbcltxh high-impedance time, bclk low to x high if fs x low, or fs x bclk high to x high if fs x high 15 60 ns tfxhdxv delay time, fs x/r high to data valid load = 100 pf plus two lsttl loads, applies if fs x/r rises later than bclk rising edge in nondelayed-data mode only 80 ns tdrvbcl setup time, d r 0/1 valid to bclk low 30 ns tbcldrx hold time, bclk low to d r 0/1 invalid ?0 to 0 15 ns 0 to 85 20 ns tbclmch bclk low to mclk high at the end of the first data bit period 50 ns ts ts ts ts
22 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 timing characteristics (continued) 5-2789 (c) note: bit 1 = sign bit. figure 4. nondelayed-data timing mode 5-2790 (c) note: bit 1 = sign bit. figure 5. delayed-data timing mode mclk (mc) bclk (bc) fs x (fx) d x 0/1 (dx) fs r (fr) d r 0/1 (dr) ts x 0/1 (tx) 12 3 4 56789 tmchmcl tmclmch tbclbch tbchbcl tbcl2bcl1 tbch1bch2 tmcl2mcl1 tbclmch tmch1mch2 tbclfxl tfxhbcl tbchdxv tfxhdxv tbchtxl tbchtxl tbclfrl tfrhbcl tdrvbcl tbcldrx tbcldxz tbcltxh 12 34567 8 12345678 mclk (mc) bclk (bc) fs x (fx) d x 0/1 (dx) fs r (fr) d r 0/1 (dr) ts x 0/1 (tx) tbchbcl 12 3 4 5789 tmcl2mcl1 tbclmch tmch1mch2 tbchtxl tdrvbcl tbcldrx tbcltxh 12345678 1 2345678 tbch1bch2 tbcl2bcl1 tmchmcl tmclmch 6 tbclbch tbcldxz tbclfrl tbchdxv tbclfxl tfrhbcl tfxhbcl
23 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter timing characteristics (continued) table 21. serial control port timing (see figure 6.) table 22. interface latch timing (see figure 6.) table 23. master reset pin symbol parameter test conditions min max unit fcclk frequency of cclk 2048 khz tcchccl time of cclk high measured from v ih to v ih 160 ns tcclcch time of cclk low measured from v il to v il 160 ns tcch1cch2 rise time of cclk measured from v il to v ih 50 ns tccl2ccl1 fall time of cclk measured from v ih to v il ?0ns tcclcsl hold time, cclk low to low measured from ?st cclk low transition 10 ns tcclcsh hold time, cclk low to high measured from eighth cclk low transition 100 ns tcslcch setup time, transi- tion to cclk low ?0ns tcshcch setup time, transi- tion to cclk high ?0ns tcivccl setup time, ci data in to cclk low ?0ns tcclcix hold time, cclk low to ci invalid ?0ns tcchcov delay time, cclk high to co data out valid load = 100 pf plus 2 lsttl loads 80 ns tcslcov delay time, low to co valid applies only if separate used for byte 2 80 ns tcshcoz delay time, high to co high impedance applies when high occurs before ninth cclk high 15 80 ns symbol parameter test conditions min max unit tilxccl setup time, il to eighth cclk of byte 1 interface latch inputs only 100 ns tcclilx hold time, il valid from eighth cclk low (byte 1) ?0ns tcclilv delay time cclk 8 of byte 2 to il interface latch outputs only c l = 50 pf 200 ns symbol parameter min max unit tmrhrml duration of master reset high 1 m s cs cs cs cs cs cs cs cs
24 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 timing characteristics (continued) 5-2791 (c) figure 6. serial control port timing cclk (cc) ci: byte 1 & byte 2 when input to ci co: byte 2 when output from co (co) il5?l0 (il) cs 1 2 345678 123 456 78 76543210 7654321 0 7654 3 2 1 0 tcclcsl tcslcch tcivccl tcclcix tcchccl tcclcch tcclcsl tcclcsh tcslcch tcch1cch2 tccl2ccl1 tcclcsh tcclilv outputs only byte 2 tilxccl tcclilx inputs only tcshcch tcslcov tcchcov tcshcoz
25 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter applications figure 7 illustrates a T7570 codec interfaced to a lucent l7554 slic. interface components were chosen for a basic 600 w resistive only termination and balance network. overall receive path gain is 0 db (pcm to t/r). overall transmit path gain is ? db (t/r to pcm). codec receive gain is 0 db. the signal level returned to vf x i is ?.658 dbm. this satis?s the transmission level point requirement for hybrid cancellation. that is, the signal at vf x i relative to the output at vf r o must be within ?.5 db to ?0.25 db. transmit gain of the codec is set at +1.658 db in order to achieve a transmission level point at dx of ? dbm. transmit and receive paths are capacitively coupled to accommodate different slic and codec bias levels. the codecs inputs are self-biased so that no additional external resistors are necessary with ac coupling. capacitor values are sized appropriately to pass low-frequency requirements of relevant gain versus frequency templates. resistive values were ascertained from slic documentation. an optional 20 k w resistor from rcvn to ground and a 30 pf capacitor across rgp can be added for stability. gain and hybrid-balance register values are shown in hex. gain values were obtained from tables 8 and 9. hybrid- balance values were obtained by removing the codec and inserting a network analyzer to measure the phase and gain returned by the loop to vf x i when a signal is injected at vf r o. gain and phase are then measured at 14 fre- quencies. the results obtained from this exercise are plugged into the hybrid-balance software that provides the register settings as shown. 5-4716.a c figure 7. 600 w resistive slic interface register settings register register number value description rx gain 04 ae 0 db tx gain 05 ae 1.658 db hybrid 1 06 a4 hybrid 2 07 51 hybrid 3 08 88 l7554 rgp 20 k w cc1 0.47 ? vitr crcv1 0.1 ? vf x i vfro 2.4 v T7570 rrcv 48.7 k w rt1 86.6 k w rcvn rcvp rpt 35 w tz 600 w rpt 35 w slic codec pt pr see register settings below
26 lucent technologies inc. T7570 programmable pcm codec data sheet with hybrid-balance filter october 1996 outline diagram 28-pin plcc dimensions are shown in inches. 5-2608r.4 1.27 typ 0.53 max 4.57 max 0.10 seating plane 0.51 min typ 12 18 11 5 4126 25 19 11.58 max 12.57 max 11.58 max 12.57 max pin #1 identifier zone
27 lucent technologies inc. data sheet T7570 programmable pcm codec october 1996 with hybrid-balance filter ordering information device code package temperature comcode t - 7570 - - - ml2 28-pin plcc ?0 c to +85 c 107055782 t - 7570 - - - ml2 -tr 28-pin plcc, tape and reel ?0 c to +85 c 107056525
for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro u.s.a.: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103, 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106), e-mail docmaster@micro.lucent.com asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 for data requests in europe: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 for technical inquiries in europe: central europe: (49) 89 95086 0 (munich), northern europe: (44) 1344 865 900 (bracknell uk), france: (33) 1 47 67 47 67 (paris), southern europe: (39) 2 6601 1800 (milan) or (34) 1 807 1700 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ?1996 lucent technologies inc. all rights reserved printed in u.s.a. october 1996 ds96-223alc (replaces ds92-224tcom and ay93-026tcom)

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